The detector forms a first partial circuit (A) which includes a delay element (3) and no more than five gates (1,2,7,8,9). The detection circuit also has a second partial circuit (B). Signals (k,e,f) from the first partial circuit (A) are fed to the second (B). The second partial circuit (B) includes a further delay element (6) and no more than four gates (4,5,10,11). The second partial circuit (B) may include an equivalence gate (4). The signal (e) from the first circuit (A) is the input signal fed to the D input and the first circuit signal (f) is fed to the Q output of a flip-flop (3). The output signal (g) of the equivalence gate (4) is used to obviate at least one gate of the first circuit (A).
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