Locking comparator with suppression of the offset voltage.

摘要

PURPOSE:To improve and compensate an offset voltage during comparation operation by storing offset information in two capacitors during offset sampling. CONSTITUTION:The both sources of electric field effect transistors Q2 and Q3, which form a first differential pair, and connected to an N-channel electric field effect transistor Q1 which is a common constant current source. Then, the transistor Q1 is controlled by a bias voltage input BI. Since an inverted input IN is the offset sampling, the input is executed through an N-channel electric field effect transistor Q9 to the gate of the electric field effect transistor Q3 as well. When a high level is given to a clock inverted input EN, the N- channel transistor Q9 is turned on and a gate input IP of the electric field effect transistor Q3 goes to be the same level as the inverted input IN. Then, the offset sampling can be executed. Thus, the offset voltage can be easily compensated without increasing die cost.