Layout design to eliminate process antenna effect

摘要

A multi-level conductive interconnection for an integrated circuit is formed in a silicon substrate, wherein there are large contact pad areas at the periphery of the interconnection. A patterned layer of a conductive polysilicon is formed on the substrate to act as a first conductive contact to the integrated circuit. An insulating layer is formed over the polysilicon layer, and openings to the polysilicon layer are formed through the insulating layer. A first layer of metal is formed on the insulator such that the metal electrically connects to the polysilicon through the openings, and also forming large contact pad areas. The first metal is patterned to form an electrical break between the large contact pad areas and the integrated circuit. This break prevents electrical damage to the integrated circuit due to charge build- up during subsequent processing in a plasma environment. A second insulating layer is formed and patterned to provide openings for vias to the first metal layer. A second layer of metal is formed over the large contact pad area and over the electrical break such that the second metal electrically connects to the first metal, via direct contact to the first metal at the large contact pad area, and through the openings in the second insulator to the first metal interconnection. Finally, a passivation layer is formed over the second metal layer.