Automated circuit design system and method for reducing critical path delay times

摘要

A computer aided design system automatically modifies a specified circuit netlist to reduce signal delays on critical signal paths. A critical signal path that does not meet specified timing constraints is identified by computing signal slack values for each node, where negative slack values indicate a failure to meeting timing requirements. Critical gates along the critical signal path that are candidates for duplication are identified by determining which critical gates have a fanout greater than one and can be represented by library cells compatible with the next circuit tree along the critical signal path. One such gate is selected and duplicated, with one copy of the duplicated output gate being used to generate only the signal on the critical signal path and the other copy of the duplicated output gate being used to drive all other fanouts of the selected gate. This generates a modified circuit netlist. Then slack values for the modified circuit netlist are compared with those of the previous version of the circuit netlist. If the slack values of circuit on the critical path have been improved, the modified circuit netlist is adopted as the current circuit netlist. If any node in the adopted circuit netlist has a negative slack value, the circuit netlist modification procedure is repeated until either no node has a negative slack, or the process is unable to further improve the slack values of the circuit netlist.