Processor having a stall cache and associated method for preventing instruction stream stalls during load and store instructions in a pipelined computer system

摘要

A central processing unit of a computer system which has an arithmetic logic unit, a register file, an instruction decode/fetch instruction data unit, a bus interface, a multiplexer and a stall cache. The stall cache is coupled to the instruction decode/fetch instruction data unit by a data bus and an internal instruction bus, so that the stall cache can receive and store instructions that have been delayed by an external data fetch during a load or store operation. Upon the next data access, the stall cache allows the delayed instruction to be accessed by the internal instruction bus and to then be processed by the central processing unit without the delay of an external data fetch.