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Fault simulator comprising a signal generating circuit implemented by hardware
Fault simulator comprising a signal generating circuit implemented by hardware
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机译:故障模拟器,包括由硬件实现的信号产生电路
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摘要
In a fault simulator for simulating a logic circuit model which is operable in response to first through n-th input pattern signals, a signal generating circuit implemented by hardware generates the first through the n-th input pattern signals. The logic circuit model is assorted into first through m-th levels and is defined by first through p- th faults. The fault simulator carries out a plurality of simulations at the same time in each of the first through the m-th levels. When the simulation proceeds to the m-th level, the fault simulator produces a simulation result signal representative of detected faults and a correct value. The fault simulator simulates the first through the p-th faults by the use of each of the first through the n-th input pattern signals.
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