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Incremental logic synthesis system for efficient revision of logic circuit designs
Incremental logic synthesis system for efficient revision of logic circuit designs
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机译:高效逻辑电路设计的增量逻辑综合系统
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摘要
An apparatus and method for incremental logic synthesis that transforms a revised technology-independent electronic digital circuit design into a revised technology-dependent design deviating as little as possible from the original technology-dependent design. The incremental synthesis procedure includes a forward sweep technique where nodes in the revised technology-independent model and the original technology- dependent design are compared to see if they map the same logical function of the inputs common to both designs. A backward sweep technique compares nodes in the revised technology-independent model to the unrevised technology-dependent design to see which outputs common to both map the same logical node functions. Portions of the revised technology- independent model with the same logical function as corresponding parts of the unchanged technology-dependent design are progressively eliminated, reducing the revised technology-independent design to an "increment" that is then conventionally synthesized and merged with the unchanged technology-dependent design to yield the revised technology-dependent design having only the minimal necessary revisions.
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