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Static random access memory which has a pair of thin film transistors and wherein the capacitance and resistance between the gate electrodes and the conductor layers are increased so as to reduce the time constant between them
Static random access memory which has a pair of thin film transistors and wherein the capacitance and resistance between the gate electrodes and the conductor layers are increased so as to reduce the time constant between them
A static random access memory of the thin film transistor load type which is enhanced in soft error resistance without involving an increase of the area of a cell is disclosed. A conductor layer is connected to the gate electrode of a first one of a pair of thin film transistors which serve as load means of each cell and is formed as a different layer from the first thin film transistor. The conductor layer is layered on a conductor layer of the other second thin film transistor with an insulating layer interposed therebetween to form a coupling capacity between the conductor layer connected to the gate electrode of the first thin film transistor and the conductor layer of the second thin film transistor. Resistors are interposed between the gates and active layers of the first and second thin film transistors and storage nodes connected to the first and second thin film transistors.
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