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Lay-out structure of power source potential lines and grand potential lines for semiconductor integrated circuit

机译:半导体集成电路的电源电位线和大电位线的布局结构

摘要

Among power supply lines for the standard cells provided nearby the corner part of an outer peripheral power supply line (the grand potential, for example) of a macro cell, the power supply line of the power source potential, for example, is connected to an inner peripheral power supply line (the power source potential) through an auxiliary power supply line provided on said corner part. The auxiliary power supply line is formed in L-shape with the first metal layer line and the perpendicular extending second metal layer line connected each other through a contact. Further, the first metal layer line of the auxiliary power supply line is provided so as to cross over the second metal layer line of the outer peripheral power supply line with an insulating layer therebetween. Therefore, the auxiliary power supply line can connect the inner peripheral power supply line and the power source potential line for the standard cell without electrical contact with the outer peripheral power supply line. Therefore, according to the present invention, all of the power supply lines can be connected each other by the automated lay-out technique without occurrence of short and manual modification, therefore the time course required for semiconductor integrated circuit development can be shortened.
机译:在宏单元的外周电源线(例如,大电位)的拐角部附近设置的标准单元的电源线中,例如,电源电位的电源线连接于电源。内周边电源线(电源电位)通过设置在所述角部的辅助电源线。辅助电源线形成为L形,其中第一金属层线和垂直延伸的第二金属层线通过触点彼此连接。此外,设置辅助电源线的第一金属层线以使其与外围电源线的第二金属层线交叉,并在它们之间具有绝缘层。因此,辅助电源线可以在不与外周电源线电接触的情况下连接内周电源线和标准单元的电源电位线。因此,根据本发明,可以通过自动布局技术将所有电源线彼此连接,而不会发生短暂和手动的修改,因此可以缩短半导体集成电路开发所需的时间。

著录项

  • 公开/公告号US5442206A

    专利类型

  • 公开/公告日1995-08-15

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号US19940240549

  • 发明设计人 TOMOKO KAI;TAKASHI IENAGA;

    申请日1994-05-11

  • 分类号H01L27/02;H01L27/10;H01L23/48;

  • 国家 US

  • 入库时间 2022-08-22 04:04:31

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