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Method and arrangement for multiplying a binary input signal by a tap coefficient in a transposed digital FIR filter and method for designing a transposed digital filter
Method and arrangement for multiplying a binary input signal by a tap coefficient in a transposed digital FIR filter and method for designing a transposed digital filter
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机译:在转置数字FIR滤波器中将二进制输入信号乘以抽头系数的方法和装置以及设计转置数字滤波器的方法
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摘要
The invention relates to a method and an arrangement in a transposed digital FIR filter for multiplying a binary input signal by tap coefficients, and to a method for designing such a filter. The invention comprises a shift register (51, 52) shifting in the direction of the least significant bit and copying the most significant bit or filling in zero values. The register receives the binary input signal of the filter and has outputs for outputting the content of the desired bit positions. A plurality of bit-serial subtractor and adder elements (53-57) multiply the binary input signal by N+1 different tap coefficients by combining output bits of the shift register (51, 52). The subtractor and/or adder elements form a network wherein at least one element participates in the multiplying operation of at least two different tap coefficients.
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