首页> 外国专利> THREE-DIMENSIONAL INTEGRATED LATCH AND BULK PASS TRANSISTOR FOR HIGH DENSITY FIELD RECONFIGURABLE ARCHITECTURE

THREE-DIMENSIONAL INTEGRATED LATCH AND BULK PASS TRANSISTOR FOR HIGH DENSITY FIELD RECONFIGURABLE ARCHITECTURE

机译:用于高密度现场可重构体系结构的三维集成闩锁和块状晶体管

摘要

PROBLEM TO BE SOLVED: To provide high-speed, high-density three-dimensional structure by providing a latch circuit in a polycrystalline silicon or an SOI layer, and arranging a pass-transistor in a single-crystal silicon region in a way that the pass- transistor is turned on or off according to the state of the latch. ;SOLUTION: A three-dimensional structure includes bulk silicon or single- crystal silicon 17 and a polysilicon layer or an SOI 19 thereon. A pass-transistor 11 is provided in the bulk silicon 17, while a latch 1 is provided in the polysilicon layer 19. In operation, the transistor 11 is turned on and off according to the state of the latch 1. The transistor 11 is turned on, when the latch 1 sends a high level signal to the gate thereof, and thereby a short circuit is provided between a metallic conductor 13 and a metallic conductor 15. The transistor 11 is turned off, when the latch 1 sends a low level signal to the gate thereof.;COPYRIGHT: (C)1996,JPO
机译:解决的问题:提供高速,高密度的三维结构,方法是在多晶硅或SOI层中提供一个锁存电路,并在单晶硅区域中布置一个传输晶体管,使得传输晶体管根据锁存器的状态导通或关断。 ;解决方案:三维结构包括块状硅或单晶硅17以及在其上的多晶硅层或SOI 19。在体硅17中设置有通过晶体管11,而在多晶硅层19中设置有闩锁1。在操作中,根据闩锁1的状态使晶体管11导通和截止。使晶体管11导通。当锁存器1向其栅极发送高电平信号时,从而在金属导体13和金属导体15之间形成短路。当锁存器1发送低电平信号时,晶体管11截止。版权归(C)1996,JPO

著录项

  • 公开/公告号JPH08241957A

    专利类型

  • 公开/公告日1996-09-17

    原文格式PDF

  • 申请/专利权人 TEXAS INSTR INC TI;

    申请/专利号JP19960007593

  • 发明设计人 MALHI SATWINDER;

    申请日1996-01-19

  • 分类号H01L27/00;G06F7/00;H01L21/8234;H01L27/088;H01L29/786;

  • 国家 JP

  • 入库时间 2022-08-22 04:03:28

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号