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CONTROL CIRCUIT FOR ASSOCIATIVE MEMORY AND THE ASSOCIATIVE MEMORY

机译:关联记忆的控制电路和关联记忆

摘要

PURPOSE: To reduce the dissipation power. ;CONSTITUTION: A timing control signal SR is set to a low level to turn on a P-MOSFET 62 and to turn ff an N-MOSFET 60, and the potential VMATCH1 of NOT circuit 64 side of a matching line is pulled up to a power source voltage VDD at the N-MOSFET 60 as a boundary. Comparison is conducted by an associative memory cell 28 during this period. The N-MOSFET 42 is turned on or off in response to the comparison result. Then, the signal SR is set to high level to turn off the P-MOSFET 62 and to turn on the N-MOSFET 60. Thus, if the N-MOSFET 42 is turned on, the potentials VMATCH1 and VMATCH are lowered to a ground level, but a through current is prevented by the off of the potential VMATCH. If the N-MOSFET 42 is off, VMATCH1 is pulled up to VDD-Vth (Vth is the threshold value voltage of the N-MOSFET60), V is maintained at VDD by NOT circuit 64 and P-MOSFET 66, and the signal representing the comparison result is output from the NOT circuit 64.;COPYRIGHT: (C)1996,JPO
机译:目的:降低功耗。 ;构成:将时序控制信号SR设置为低电平以导通P-MOSFET 62并导通N-MOSFET 60,并且将NOT电路64侧的电位VMATCH 1 匹配线在作为边界的N-MOSFET 60处被上拉至电源电压VDD。在此期间,通过关联存储单元28进行比较。 N-MOSFET 42响应于比较结果而导通或截止。然后,信号SR被设置为高电平以截止P-MOSFET 62并导通N-MOSFET60。因此,如果N-MOSFET 42导通,则电势VMATCH 1 和VMATCH降低到地电位,但是通过关闭电位VMATCH来防止通过电流。如果N-MOSFET 42截止,则VMATCH 1 被上拉至VDD-V th (V th 是阈值电压)。 N-MOSFET60),通过NOT电路64和P-MOSFET 66将V保持在VDD,并且从NOT电路64输出表示比较结果的信号。;版权所有:(C)1996,JPO

著录项

  • 公开/公告号JPH08147986A

    专利类型

  • 公开/公告日1996-06-07

    原文格式PDF

  • 申请/专利权人 INTERNATL BUSINESS MACH CORP IBM;

    申请/专利号JP19940292556

  • 发明设计人 SATO AKASHI;

    申请日1994-11-28

  • 分类号G11C15/00;

  • 国家 JP

  • 入库时间 2022-08-22 03:57:20

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