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Control circuit of associative memory and associative memory device
Control circuit of associative memory and associative memory device
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机译:关联存储器的控制电路及关联存储器
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摘要
The present invention aims to reduce power consumption.;The timing control signal SR is brought to the low level to close the P-MOSFET 62 and open the N-MOSFET 60 and to set the NOT circuit 64 of the match line on the N-MOSFET 60 as a boundary. Side potential VMATCHTo the power supply voltage VDDUp. The comparison operation is performed in the associative memory cell 28 between them, and the P-MOSFET 42 is turned on or off according to the comparison result. Next, the control signal SR is set to the high level, the P-MOSFET 62 is turned off, and the N-MOSFET 60 is turned on. Thus, when the N-MOSFET 42 is turned on, the potential VMATCHAnd potential VMATCHBut the penetration current is blocked by the P-MOSFET 62 being turned off. When the N-MOSFET 42 is turned off, VMATCHVDD-Vtn(VtnIs pulled up to the threshold voltage of the N-MOSFET 60), VMATCHMOSFET 64 by the NOT circuit 64 and the P-MOSFET 66,DDAnd the signal indicating the result of comparison is output from the NOT circuit 64. [;See FIG. 3.
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机译:本发明旨在降低功耗。将定时控制信号SR拉至低电平以关闭P-MOSFET 62并打开N-MOSFET 60,并在N-上设置匹配线的NOT电路64。 MOSFET 60作为边界。侧电势V MATCH Sub>到电源电压V DD Sub> Up。在它们之间的关联存储单元28中执行比较操作,并且根据比较结果将P-MOSFET 42导通或截止。接下来,将控制信号SR设置为高电平,P-MOSFET 62截止,并且N-MOSFET 60导通。因此,当N-MOSFET 42导通时,电势V MATCH Sub>和电势V MATCH Sub>但是,穿透电流被P-MOSFET 62截止而被阻挡。当N-MOSFET 42关断时,拉V MATCH Sub> V DD Sub> -V tn Sub>(V tn Sub>最高可达N-MOSFET 60的阈值电压),通过NOT电路64和P-MOSFET 66达到V MATCH Sub> MOSFET 64, DD Sub>,并指示结果从NOT电路64输出比较结果。 3。
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