ARBITRATION OF PACKET SWITCHED BUSSES, INCLUDING BUSSES FOR SHARED MEMORY MULTIPROCESSORS

摘要

An arbiter is provided for resolving contention on synchronous packetswitched busses, including busses composed of a plurality of pipelinedsegments, to ensure that all devices serviced by such a bus are given fair,bounded time access to the bus and to permit such devices to fill all availablebus cycles with packets. Flow control for shared memory multiprocessors isreadily implemented with this arbiter because the arbiter supports differenttypes of arbitration requests and the prioritization of such arbitrationrequests by type.