Data transfer controller using dummy signals for continued operation under insignificant faulty conditions

摘要

In a data processing system, a processor (2) issues a transfer request through a data transfer controller (1) to an extended buffer memory (4) to elicit an accept signal. If the accept signal is not returned from the buffer memory (4) within a specified period, a first dummy signal is generated instead, and the controller (1) notifies this fact to the processor (2) and waits for the return of an advance notice from the buffer memory (4). If the advance notice is not returned within a specified period, a second dummy signal is generated instead to allow the controller (1) to proceed to transfer data read out of the buffer memory (4) to a main memory (3). The controller (1) then waits for the return of a status report signal from the buffer memory (4). If the status report signal is not received within a specified period, a third dummy signal is generated instead to allow the controller (1) to proceed to examine a status signal from the buffer memory (4) to determine whether the transferred data has been correctly read out of the buffer memory (4). A reply signal is applied to the processor (2) indicating the result of determination.