Topology-based computer-aided design system for digital circuits and method thereof

摘要

A computer-aided design system and method thereof for performing logic design analysis for determining logical interdependencies between points in a digital circuit topology. Such a topology comprises a set of primary outputs and a set of primary inputs, both interconnected with logic gates. The logic gates are interconnected by wires. Each such point comprises a location on a wire carrying a signal asserted into or from one of the logic gates. A representation of such topology is stored in a storage device in the computer-aided design system. A cutset in the topology is selected comprising the logic gates falling in a fan-in of the logic gates leading to a target one of the logic gates. A decision diagram is built for logic gates in the cutset leading from the target logic gate. The logic gates in a potential learning area in the topology are marked. Justification vectors are extracted from the decision diagram for a predetermined Boolean value of the target logic gate. Such logical interdependencies are determined and a representation of the logical interdependencies is stored in a storage device in the computer-aided design system. Boolean operations are performed between the decision diagram and a plurality of other decision diagrams for the logic gates in the potential learning area.