A phase-locked loop (PLL) system clock generator that instantly shifts the clock frequency.

摘要

The present invention provides a phase locked loop (PLL) clock generator for a digital system. The PLL clock generator is capable of immediate conversion between high and low frequencies corresponding to active and slow modes, and vice versa. The PLL clock generator includes a phase lock circuit, a frequency converter coupled to the output of the phase lock circuit, and a frequency controller coupled to the frequency converter. The frequency converter may immediately convert the frequency of the first clock signal received from the phase lock circuit. The frequency controller is responsible for controlling the frequency at the output of the frequency converter. The frequency controller responds to a control signal in which the conversion of the PLL clock generator from the active mode to the slow mode and vice versa is used. In one embodiment, the phase locked circuit generates a first clock signal in response to a reference clock signal and a feedback clock signal. The frequency converter includes a first divider for generating a global clock signal in response to the first clock signal, and a second divider for generating a peripheral clock signal and a feedback signal in response to the global clock signal. The frequency controller immediately converts the PLL circuit between the active mode and the slow mode in response to a control signal used to simultaneously change the first and second divider parameters.