A device for processing branch instructions on a computer

摘要

The present invention relates to a processor capable of processing instructions of a computer program. The processor includes a next fetch address circuit for fetching instructions of the computer program and a decode circuit coupled to the next fetch address circuit and for partially decoding fetched instructions to determine whether the fetched instruction is a conditional branch. The computer is also coupled to a next fetch address circuit and also includes a first memory for storing a plurality of branch prediction entries for a conditional branch instruction of the program. The computer also includes a separate second memory for storing a plurality of intensity entries associated with the plurality of branch prediction entries in the first memory. An update circuit coupled to the first memory and the second memory is also provided for updating the branch prediction entry and the associated strength entry corresponding to each of the first and second memory after the conditional branch instruction is executed and interpreted in the pipeline computer.