A semiconductor interface circuit comprises a threshold circuit (51) supplied with an input logic signal and an internal reference signal (VMREF) for discriminating the logic level thereof, and a reference circuit (52) supplied with an external reference voltage for producing the internal reference signal. The threshold circuit comprises a first load (55), a first enhancement mode FET (56) and a second load (57) connected in series between a first power terminal (53) and a second power terminal (54), wherein the internal reference signal is supplied to the gate of the first enhancement mode FET. Further, a first FET (58) having a gate to which the input logic signal is supplied, is provided between the first and second power supply terminals. The first enhancement FET (56) produces the output at the drain thereof. The reference circuit comprises a third load (55A), a second enhancement mode FET (56A) and a fourth load (57A) connected in series between the first and second power terminals, wherein the drain and the gate are connected. Further, a second FET (58A) is provided across the first and second power terminals. The second FET is supplied with the reference voltage at a gate thereof, and the internal reference voltage is obtained at the drain of the second enhancement mode FET. IMAGE
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