Digital voltage-controlled oscillators.

摘要

PURPOSE:To vary an output in a smaller phase chip than a phase pitch corresponding to a clock frequency. CONSTITUTION:A PLL in which a VCO is adopted for a ring oscillator 1 is formed and an output tap among output taps (1)-(15) of the said ring oscillator 1 is selected repetitively to rotate the phase, then a frequency of a signal Vp extracted from the said ring oscillator 1 is changed minutely to obtain the output Vp in a far smaller phase pitch than the oscillation period of the ring oscillator 1.