A device for optimizing the performance of a processor.

摘要

The device according to the invention uses at least two blocks read-only memories (mp, mi) containing the instructions of the application code, and the addressing inputs are respectively connected to two counters (cp, ci) connected to the address bus (ab) of the microprocessor (mup). The outputs of the reading of these blocks are connected to the data bus of the microprocessor (mup) by means of two barriers (bp, bi). A control circuit (r, lc) is provided to control, as a function of the nature of the addresses issued on the address bus (ab) and at the rate of those - latter, a succession of cycles each comprising the transfer on the data bus (db), via one or other of the barriers (bp, bi), the data contained in one or other of the memories (mp) or mi) and the incrementation of the counter associated with the other memory (m1, mp), so as to anticipate the transfer of data which will be carried out at the next cycle. & br / the invention applies in particular to the on-board processors on board an aircraft.