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Power and time saving initial tracebacks

机译:省电省时的初始回溯

摘要

A digital communication system including a Viterbi decoder for tracing a path through a trellis of individual state information and method of operation are disclosed. The traceback determines a decoded symbol. A trellis of branch origin data is stored in an array of registers. The branch origin data associated with a symbol instant is a cell. Each cell of data is generated by execution of an update instruction form a digital signal process (DSP) to the coprocessor. A first predetermined traceback length is written to a traceback length register. The first predetermined traceback length is small to minimize tracebacks cycling into branch origin data from a previous transmission burst. A traceback is initiated by the DSP providing the coprocessor a single traceback instruction. The Viterbi decoder alternates between update and traceback instructions. At a predetermined symbol instant, the traceback length is increased to a second predetermined length by over- writing the traceback length register. The second predetermined length is selected relative to the predetermined symbol instant to assure tracebacks do not cycle into branch origin data from a previous transmission burst. After all updates are complete, the update instruction is omitted and the traceback instruction repeatedly executed until all symbols from a transmission burst are decoded.
机译:公开了一种包括维特比解码器的数字通信系统和操作方法,该维特比解码器用于跟踪通过各个状态信息的网格的路径。追溯确定已解码符号。分支原始数据的网格存储在寄存器数组中。与符号瞬间关联的分支原始数据是一个单元。每个数据单元都是通过执行更新指令来生成的,该更新指令是通过数字信号处理(DSP)发送给协处理器的。将第一预定回溯长度写入回溯长度寄存器。第一预定回溯长度小以最小化回溯循环到来自先前传输突发的分支原始数据中的回溯。 DSP向协处理器提供单个回溯指令来启动回溯。维特比解码器在更新和追溯指令之间交替。在预定的符号时刻,通过重写回溯长度寄存器将回溯长度增加到第二预定长度。相对于预定符号时刻选择第二预定长度,以确保回溯不循环到来自先前传输突发的分支原始数据中。在完成所有更新之后,将省略更新指令,并重复执行回溯指令,直到对来自传输突发的所有符号进行解码为止。

著录项

  • 公开/公告号US5490178A

    专利类型

  • 公开/公告日1996-02-06

    原文格式PDF

  • 申请/专利权人 AT&T CORP.;

    申请/专利号US19930153333

  • 申请日1993-11-16

  • 分类号H04L27/06;H03M13/12;

  • 国家 US

  • 入库时间 2022-08-22 03:39:03

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