Apparatus for multiport memory access control unit with plurality of bank busy state check mechanisms employing address decoding and coincidence detection schemes

摘要

A memory access control unit in a data processing apparatus. The memory access control unit includes memory unit has a plurality of memory ports. Each of the memory ports connects to plurality of memory banks. The memory access control unit has a circuit for allocating in advance the memory addresses to be accessed among the corresponding memory ports. By utilizing this circuit, a group of memory bank addresses in a busy state are registered for each memory port of the memory unit, and this group of memory bank addresses in a busy state are compared with the memory addresses to be accessed. As a result of this comparison, it is judged whether or not the memory banks to be accessed are in a busy state.