Control of access to an external interface by an IMBUS and MIL-BUS simultaneously accessing the interface dual port ram, whereby a MIL-BUS control mechanism checks for an IMBUS busy signal prior to MIL-BUS transmission

摘要

Method for resolution of busy problems occurring when an IMBUS and MIL-BUS simultaneously access a dual port ram (DPR) includes the following steps: determination of access priorities, control of the MIL-BUS access to the DPR by means of a special MIL-BUS control mechanism that has a one MHz reference clock signal and avoidance of access conflicts with the IMBUS by checking for an IMBUS busy signal before each data transfer.