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System and method for controlling the competition between processors, in an at-compatible multiprocessor array, to initialize a test sequence

机译:用于在兼容的多处理器阵列中控制处理器之间竞争以初始化测试序列的系统和方法

摘要

A multiprocessor array where any single multiprocessor can be needed to execute a prescribed sequence and more than one of the processors may compete to initialize this sequence, and wherein a "semaphore port" SP is coupled to all processors, this port SP being adapted to normally signal "GO", but after "first-access" by a said processor, which thus becomes a "selected processor", to thereupon signal "STOP" to all other, "non- selected", processors, and so deny access until a given test sequence is completed.
机译:一种多处理器阵列,其中可能需要任何单个多处理器来执行规定的序列,并且不止一个处理器可以竞争初始化该序列,并且其中“信号量端口” SP连接到所有处理器,该端口SP通常用于信号“ GO”,但在所述处理器(因此成为“选定处理器”)进行“首次访问”之后,便向所有其他“非选定”处理器发出信号“ STOP”,因此拒绝访问直到给定的测试顺序已完成。

著录项

  • 公开/公告号US5524209A

    专利类型

  • 公开/公告日1996-06-04

    原文格式PDF

  • 申请/专利权人 PARKER;ROBERT F.;GUPTA;ANIL K.;

    申请/专利号US19950396402

  • 发明设计人 ANIL K. GUPTA;ROBERT F. PARKER;

    申请日1995-02-27

  • 分类号G06F11/00;

  • 国家 US

  • 入库时间 2022-08-22 03:38:29

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