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System and method for controlling the competition between processors, in an at-compatible multiprocessor array, to initialize a test sequence
System and method for controlling the competition between processors, in an at-compatible multiprocessor array, to initialize a test sequence
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机译:用于在兼容的多处理器阵列中控制处理器之间竞争以初始化测试序列的系统和方法
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摘要
A multiprocessor array where any single multiprocessor can be needed to execute a prescribed sequence and more than one of the processors may compete to initialize this sequence, and wherein a "semaphore port" SP is coupled to all processors, this port SP being adapted to normally signal "GO", but after "first-access" by a said processor, which thus becomes a "selected processor", to thereupon signal "STOP" to all other, "non- selected", processors, and so deny access until a given test sequence is completed.
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