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Buffer storage system and method using page designating address and intra- page address and detecting valid data

机译:使用页指定地址和页内地址并检测有效数据的缓冲存储系统和方法

摘要

A buffer storage system and method using a page designating address and an intra-page address for information processing according to a logical address is provided. The buffer storage system includes a page designating address for designating a page in a virtual address space, and an intra-page address for indicating an address in a given page. An address supply unit for outputting an address signal comprising a portion of the page designating address and the intra-page address may be included. The buffer storage system also provides a data storage unit for storing a portion of data from a main storage in a storage location corresponding to the portion of the page designating address and the intra-page address. The buffer storage system includes a plurality of address information storage units of a number determined by the portion of the page designating address. The address information storage units store address information concerning the storage location of the part of data in a storage location designated by an address of which only a portion of the page designating address is different. The buffer storage system may also include an invalidation unit for performing, in response to a write instruction to main storage, outputs of the address information storage units and a real address corresponding to the supplied logical address, a replacement of data in the data storage unit based on supplied write data and an invalidation of an address information corresponding to the data to be replaced. Replacement and invalidation may be simultaneously performed.
机译:提供了一种缓冲存储系统和方法,其使用页指定地址和页内地址用于根据逻辑地址进行信息处理。缓冲存储系统包括用于在虚拟地址空间中指定页面的页面指定地址,以及用于指示给定页面中的地址的页面内地址。可以包括用于输出包括页面指定地址和页面内地址的一部分的地址信号的地址提供单元。缓冲存储系统还提供数据存储单元,用于将来自主存储器的一部分数据存储在与页面指定地址和页面内地址的一部分相对应的存储位置中。该缓冲器存储系统包括多个地址信息存储单元,其数量由页面指定地址的该部分确定。地址信息存储单元将与数据的一部分的存储位置有关的地址信息存储在由仅页面指定地址的一部分不同的地址指定的存储位置中。缓冲存储系统还可以包括无效单元,该无效单元用于响应于对主存储器的写指令来执行地址信息存储单元的输出以及与所提供的逻辑地址相对应的实地址,以对数据存储单元中的数据进行替换。基于提供的写数据和与要替换的数据相对应的地址信息的无效。替换和失效可以同时执行。

著录项

  • 公开/公告号US5544293A

    专利类型

  • 公开/公告日1996-08-06

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号US19940176679

  • 发明设计人 KEIZOU NOZAWA;

    申请日1994-01-03

  • 分类号G06F12/08;G06F12/10;G06F12/12;

  • 国家 US

  • 入库时间 2022-08-22 03:38:05

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