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Schematic generator and schematic generating method

机译:原理图生成器和原理图生成方法

摘要

Disclosed is here units or processing steps respectively for detecting loops in a logic circuit to determine logic levels associated with first coordinates of respective elements such that a location where the overlapping of the loops develop the maximum value is assigned as a feedback routing, for determining positional relationships between elements at the reference level to relieve congestion of routings in the vicinity of the reference level, for sequentially achieving the maximum matching on a bipartite graph constituted with connective relationships of the elements for each level beginning from the reference level to determine positional relationships related to second coordinates so as to assign elements associated with each other to the same position, and for defining virtual routing length to achieve routing in accordance with a result of sorting by use of the virtual routing lengths.
机译:在此公开了分别用于检测逻辑电路中的环路以确定与各个元件的第一坐标相关联的逻辑电平的单元或处理步骤,从而将环路的重叠形成最大值的位置分配为反馈路线,以确定位置参考级别的元素之间的关系,以缓解参考级别附近的路由的拥塞,从而在由参考级别开始的,由每个级别的元素的连接关系构成的二部图上依次实现最大匹配,以确定相关的位置关系第二坐标为第二坐标,以便将彼此相关联的元素分配给同一位置,并根据使用虚拟路由长度的排序结果来定义虚拟路由长度以实现路由。

著录项

  • 公开/公告号US5550714A

    专利类型

  • 公开/公告日1996-08-27

    原文格式PDF

  • 申请/专利权人 MATSUSHITA ELECTRIC INDUSTRIAL CO. LTD.;

    申请/专利号US19890403452

  • 发明设计人 TAMOTSU NISHIYAMA;

    申请日1989-09-06

  • 分类号G06F17/50;

  • 国家 US

  • 入库时间 2022-08-22 03:37:58

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