Low cost writethrough cache coherency apparatus and method for computer systems without a cache supporting bus

摘要

An apparatus and method for supporting a writethrough cache in a computer system not otherwise supporting cache is disclosed. Cache coherency is guaranteed by a cache coherency module detecting the CPU programming a DMA controller to allow a device other than the CPU to transfer data to main memory and, until the data transfer is concluded, flushing the cache each time the CPU reads an address other than an address of a standard computer system component. The cache is also flushed upon conclusion of the data transfer. In computer systems including a bus master device, the cache is flushed whenever the cache coherency module detects the CPU reading an address other than an address of a standard computer system component and whenever the cache coherency module detects an interrupt other than a standard computer system interrupt. The cache coherency module includes a bus snooping sub-module to snoop address, control and data on the bus; a DMA address table and a system address table to define DMA addresses, standard system component addresses and standard system interrupts; and a control logic sub-module to identify DMA programming actions, non-standard addresses and non- standard interrupts, and to issue cache flush signals. Also disclosed is an apparatus and method to automatically determine the range of cacheable addresses in the computer system and to turn on the cache after the computer system is reset.