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High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non- multiplexed external bus
High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non- multiplexed external bus
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机译:高性能集成处理器体系结构,包括子总线控制单元,用于产生信号以控制辅助的非复用外部总线
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摘要
An integrated processor that employs a bus interface unit to accommodate high performance data transfers via an external peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, accommodates data transfers between an internal bus of the integrated processor and PCI peripheral devices. The integrated processor further includes a sub-bus control unit that generates a set of side-band control signals that allow the external derivation of a lower performance secondary bus, such as an ISA bus, without requiring a complete set of external pins for the secondary bus on the integrated processor. The derivation of the secondary bus is accomplished with an external data buffer and an external address latch which are controlled by the side-band control signals. Separate address and data lines from the integrated processor for the secondary bus are not required. Accordingly, high performance peripheral devices are supported by the integrated processor as well as lower performance, lower-cost peripherals without a significant increase in the pin-count of the integrated processor. Accordingly, overall cost of the integrated processor is kept low while a wide range of peripheral devices are supported.
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