Multiplexed by-passable memory devices with increased speed and improved flip-flop utilization

摘要

A memory device, with increased storage speed and enhanced memory utilization, can be implemented by using multiplex clocking and efficient device design and enhanced flip-flop utilization. Transit time through the circuit, and hence circuit speed, can be controlled through multiplexed clock signals, and is increased by using fewer transistors in the signal path and allowing data to be transmitted directly to the flip- flop output by bypassing the flip-flop's master latch input.