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METHOD FOR DECIDING DIFFUSION RESISTANCE CALCULATING EXPRESSION FOR IMPURITY DIFFUSION LAYER IN LSI CIRCUIT DESIGN

机译:LSI电路设计中杂质扩散层的扩散电阻计算表达式的确定方法

摘要

PROBLEM TO BE SOLVED: To decide an optimum diffusion resistance calculation expression for impurity diffusion layer at the time of designing an LSI circuit. ;SOLUTION: A graphic constituting a layout L is extracted by a graphic extraction part 11. In a calculation expression storing table T, plural calculation expressions for calculating the diffusion resistance of impurity diffusion layer are prepared and each calculation expression is successively selected by a calculation expression selection part 13 to be given to a parameter extraction part 12. The parameter extraction part 12 applies the respective calculation expressions to a graphic constituting the impurity diffusion layer to obtain a diffusion resistance value as a parameter. A net list N is prepared through the use of this parameter and circuit simulation is executed by a circuit simulator 20 to obtain a delay time as a characteristic value V. On the other hand, an actual device is produced based on the layout L to obtain the device measurement value M of the delay time to select the characteristic value V closest to this measured value M by a comparator 30 and the calculation expression used to obtain the selected characteristic value V is decided to be the optimum calculation value.;COPYRIGHT: (C)1997,JPO
机译:解决的问题:在设计LSI电路时,确定杂质扩散层的最佳扩散电阻计算表达式。 ;解决方案:由图形提取部分11提取构成布局L的图形。在计算表达式存储表T中,准备了多个用于计算杂质扩散层的扩散电阻的计算表达式,并通过计算依次选择了每个计算表达式表达式选择部分13将被提供给参数提取部分12。参数提取部分12将各个计算表达式应用于构成杂质扩散层的图形,以获得作为参数的扩散阻力值。通过使用该参数来准备网表N,并且由电路模拟器20执行电路模拟以获得作为特性值V的延迟时间。另一方面,基于布局L生产实际装置以获得通过比较器30选择最接近该测量值M的特征值V的延迟时间的设备测量值M和用于获得选择的特征值V的计算表达式被确定为最佳计算值。 1997)日本特许厅

著录项

  • 公开/公告号JPH09128433A

    专利类型

  • 公开/公告日1997-05-16

    原文格式PDF

  • 申请/专利权人 DAINIPPON PRINTING CO LTD;

    申请/专利号JP19950302127

  • 发明设计人 SATO HIDEKI;NARA HIDEYUKI;

    申请日1995-10-26

  • 分类号G06F17/50;H01L27/04;H01L21/822;

  • 国家 JP

  • 入库时间 2022-08-22 03:36:35

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