INSTRUCTION PREFETCH BUFFER CONTROL METHOD AND DEVICE THEREFOR AND INSTRUCTION PREFETCH BUFFER FLUSH METHOD

摘要

PROBLEM TO BE SOLVED: To increase the sequential execution speed of normal instructions and to improve the overall multi-thread operation efficiency for a multi-thread processor. ;SOLUTION: An IPB(instruction prefetch buffer) control part 101 inputs the PC value 126 of a PC(program counter) generation part 125, the branch condition signal 127 of a DEC(decoder) part 114, the branch satisfaction signal 117 outputted from a branch satisfaction decision part 116, the instruction issue signal 102 outputted from a PL(pipeline) control part 124, and the branch destination detection signal 123 and the IF(instruction fetch) data valid signal 107 which are outputted from an IF part 106 respectively. Then the part 101 outputs the IPB valid signal 120, IBP updating signal 108, NRP(next read pointer) signal 122, and CRP(current read pointer) signal 103. A delay instruction detection part 115 inputs the signals 117, 120 and 122 and decides whether a delay instruction is included in the IB 105 that is pointed by the NRP.;COPYRIGHT: (C)1997,JPO