GEOMETRICAL ARRANGEMENT OF FALSE TRANSISTOR AGAINST REVERSE ENGINEERING AND DIGITAL CIRCUIT PROVIDED WITH CHANNEL STOP

摘要

PROBLEM TO BE SOLVED: To inhibit reverse engineering of an integrated circuit by arranging different logic cells in substantially the same spatial patterns and making the logical functions of the cells not distinguishable from a transistor pattern, and then, deciding the logical function of the cells by the pattern of conductive ion implantation interconnections. ;SOLUTION: All p-channel transistors 2-6 and n-channel transistors 12-16 in an array have substantially the same sizes and geometric structures. Interconnections are performed through the injection of a doping impurity into the substrate between desired source and drain. In other words, the implanting sections of the source and drain are expanded on either one side section of a transistor provided with a tap including a source tap ST and a drain tap DT and the interconnection is executed by using the tap and its adjacent connector C. Therefore, the reverse engineering of an integrated circuit can be prevented.;COPYRIGHT: (C)1997,JPO