HARMONIZED SOFTWARE CONTROL FOR HARDWARE ARCHITECTURE CACHE MEMORY USING PREFETCH INSTRUCTION

摘要

PROBLEM TO BE SOLVED: To reduce slashing by writing both an instruction and data in a proper cache. SOLUTION: Prefetch instructions 24 including a binary field provide prefetch hardware equipped with information regarding an optimum cache set position to be prefetched and an optimum data amount. The Harvard architecture provided with the different instructions and data caches is supported under different software control over the instructions and data caches. A cache set number is discriminated so as to indicate which set information should be preloaded to. The size field provides variable prefetch size. An address field shows the address where the prefetch starts.