Coded manner and memory system null for single subblock error and single bit error

摘要

In accordance with a preferred embodiment of the present invention, a mechanism is provided for converting Type II binary parity check matrices for a large class of codes into a larger parity check matrix which is more suitable for error detection and correction in memory systems which employ multiple bit per chip output architecture. More particularly, the present coding method provides codes which exhibit check bit requirements which are less than those for a Type II code but greater than those for a Type I code. In particular, the codes of the present invention are capable of detecting all combinations of a single symbol error and a single bit error. In addition, the codes for the present invention exhibit all of the correction and detection properties for a Type I code but do not rise to the capabilities or the complexities of Type II codes which are capable of correcting all single symbol errors and detecting all double symbol errors. In particular, the present invention avoids the weakness found a in Type I code which occurs in those situations in which there is a symbol error from a symbol bit group and another error from a different symbol.