Statistical parasitism resistant and parasitic capacity model device

摘要

PURPOSE:To efficiently extract parasitic element information by the minimum quantity of manual work by extracting parasitic elements such as parasitic resistance, parasitic capacity and inter-wire capacity from real circuit layout pattern data and real circuit diagram data by a statistic method and modeling the extracted contents. CONSTITUTION:This modeling device is provided with a means 1 for extracting the length of a real wiring and the length of a parallel real wiring having a wiring appearing in parallel with the real wiring from real circuit layout pattern data D0, a means 7 for extracting the real wiring length from the data D0 and statistically estimating the length of a parallel virtual wiring whose wiring is supposed to appear in parallel with the real writing and a means 9 for extracting the number of fan-outs in each wiring from real circuit diagram data D1, statistically estimating the length of a supposed virtual wiring and statistically estimating the length of a parallel virtual wiring whose wiring is supposed to appear in parallel with the real wiring. Thus, the virtual wiring length and the parallel virtual wiring length can be statistically found out based on the real circuit data such as the real circuit layout pattern data and the real circuit diagram data and parasitic element information such as parasitic element characteristic value can easily be obtained.