A METHOD OF TESTING A MEMORY ADDRESS DECODER AND A FAULT-TOLERANT MEMORY ADDRESS DECODER

摘要

Hard-open defects between logic gates ofan address decoder and the voltage supply ren-der a memory conditionnally inoperative. Thedecoders are therefore examined for such hard-open defects. Two cells of two logically ad-jacent rows or columns are written with com-plementary logic data. If a Read operation re-veals the data in the two cells to be identical,the presence and location of a hard-open defectin the decoders is demonstrated. Alternatively,the memory is provided with a fault-tolerant de-coder that comprises additional disabling meansto properly disable the rows and columns evenwhen a hard-open defect is present in the de-coders' logic gates.