VARIABLE DELAY LINE OF WIDE MARGIN AND RING OSCILLATOR.

摘要

A VARIABLE DELAY LINE (10) THAT HAS A SERIES OF "SLOW" LOGIC INVERTERS AND AN EQUAL NUMBER OF "FAST" INVERTERS (14) WITH CONNECTED INPUTS TO MATCH THE "SLOW" INVERTER INPUTS. THE TRANSMISSION DOORS (15) THAT COUPLES THE "FAST" INVERTER OUTPUTS TO MATCH THE "SLOW" INVERTER OUTPUTS, VARY THE COUPLING AMOUNTS BETWEEN THE INVESTORS. THE MAXIMUM DELAY IS SUBSTANTIALLY GIVEN WITH A NON-COUPLING BETWEEN "QUICK" AND "SLOW" INVESTORS AND THE MINIMUM DELAY IS GIVEN WHEN THE MAXIMUM COUPLING OCCURS BETWEEN "FAST" AND "SLOW" INVESTORS. THE VARIABLE DELAY LINE CAN BE CONFIGURED WITHIN A VARIABLE FREQUENCY RING OSCILLATOR USEFUL IN SYNCHRONIZED OR SIMILAR LOOPES.