Capacitively coupled successive approximation ultra low power analog-to-digital converter

摘要

A capacitively-coupled successive approximation analog-to-digital converter utilizes a capacitively coupled multiplying digital to analog converter to generate a succession of voltages which are compared to the input voltage to be digitized. The capacitively coupled multiplying digital to analog converter generates the required succession of analog voltage levels utilizing very low power in response to digital signals. A double-sided version of the invention processes differential inputs with improved common-non-ideality mode rejection.