INPUT RECEIVER, OUTPUT DRIVER, AND INPUT/OUTPUT DRIVER CIRCUITS CAPABLE OF HIGH VOLTAGE OPERATION FOR AN INTEGRATED CIRCUIT

摘要

An output driver circuit and an input receiver circuit are provided. The output driver circuit employs a series-connected pair of PMOS transistors (102) and coupled to a series-connected pair of NMOS transistors (106, 108). One of the PMOS transistors (102) and one of the NMOS transistors (106) have their gate terminals connected to a pair of power sources (Vref, VCC) such that these transistors maintain a voltage level on the node connecting the transistor to its corresponding pair. The voltage level is maintained during times when the pair of transistors are not conducting current. By maintaining this voltage, the voltage difference between any two terminals of the transistors is held within the maximum allowable voltage of the semiconductor technology. An input receiver circuit is also described which contains an NMOS transistor (120) between the input conductor and receiving inverter circuits. This NMOS transistor (120) has its gate terminal connected to a power supply (VCC) conveying the same voltage as the power supply for the integrated circuit core. The NMOS transistor (120) limits the voltage at the input of the receiving inverter circuits to no more than the power supply voltage (VCC). The circuits may be combined to form an input/output driver circuit.