High-speed multiplier for a microcomputer used in a digital signal processing system

摘要

A multiplier using Booth's algorithm for multiplying first and second input binary coded numbers has a plurality of decoders each responsive to a pair of adjacent bits of the first input number to produce a control signal, a plurality of static adder levels respectively responsive to the control signals from the decoders and each including a plurality of parallel binary adder stages respectively for the bits of the second input number and with n carry path, each level but the highest producing partial product and carry outputs which are connected to the next higher level, and a plurality of additional adder stages with a ripple carry path for receiving the bits of the partial products produced by the adder levels and producing a product output.