首页> 外国专利> A METHOD FOR TESTING AN ELECTRONIC CIRCUIT BY LOGICALLY COMBINING CLOCK SIGNALS, AND AN ELECTRONIC CIRCUIT PROVIDED WITH FACILITIES FOR SUCH TESTING

A METHOD FOR TESTING AN ELECTRONIC CIRCUIT BY LOGICALLY COMBINING CLOCK SIGNALS, AND AN ELECTRONIC CIRCUIT PROVIDED WITH FACILITIES FOR SUCH TESTING

机译:一种通过逻辑上结合时钟信号来测试电子电路的方法,以及一种具有进行这种测试的功能的电子电路

摘要

An electronic circuit has a plurality of nodes at which a plurality of clock signals are present in operational use. The clock signals should have a pre-determined timing relationship amongst themselves. The circuit includes logic circuitry having inputs connected to the nodes and having an output to provide a pulse train. Any discrepancy between the actual and ideal pulse trains indicates a fault.
机译:电子电路具有多个节点,在操作使用时,在多个节点处存在多个时钟信号。时钟信号之间应具有预定的定时关系。该电路包括逻辑电路,该逻辑电路的输入连接到节点并且具有输出以提供脉冲序列。实际和理想脉冲序列之间的任何差异都表明存在故障。

著录项

  • 公开/公告号EP0780037A2

    专利类型

  • 公开/公告日1997-06-25

    原文格式PDF

  • 申请/专利权人 PHILIPS ELECTRONICS N.V.;

    申请/专利号EP19960917625

  • 发明设计人 SACHDEV MANOJ;ATZEMA BOTJO;

    申请日1996-07-01

  • 分类号H03K19/00;

  • 国家 EP

  • 入库时间 2022-08-22 03:19:36

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