Memory architecture for flexible reading management, particularly for non-volatile memories, having noise-immunity features, matching device performance, and having optimized throughput

摘要

A memory architecture for flexible reading management, particularly for non-volatile memories, comprising: at least one memory matrix (1); at least one sense amplifier (7) for capturing the data from the at least one memory matrix (1); at least one output buffer (8) for providing the read data in output, connected to the sense amplifier by means of an internal bus; and at least one row decoder (3) for selecting the word lines of the memory matrix; characterized in that it furthermore comprises:-- a memory read address transition detection circuit (25), adapted to produce an address transition signal (ATD);-- a circuit (13) for enabling/disabling the read circuits;-- a circuit (11) for enabling the reading process, adapted to enable reading only after the minimum functionality levels of the memory cells involved in the reading operation and of all the connected read circuits have been reached;-- a network (12) for equalizing and correlating the reading with respect to the characteristics of the devices, the signal propagations, and the conductivity of the memory cells, the propagations being detected by a propagation reproduction circuit;-- a reading cycle end circuit (14), adapted to determine the end of the reading process by deactivating the row decoder following the capture of the read data item in the sense amplifier; and-- a circuit (15) for the synchronized and time-limited loading of the data in the at least one output buffer (8), the output buffer having a memory structure and being normally disconnected from the internal circuits, the enabling of the reading process being performed in close correlation with the intrinsic characteristics of the read circuits and of the memory cells.