The digital voice signal matching device comprises: a central processing unit (48) controlling respective organization elements through an address bus and a data bus according to a control program stored in a program memory (46) and data of a data memory (47); a switching unit (41) inputting first clocks (2MCLK and 4MCLK) and a frame synchronizing signal (FS) from an outside according to the central processing unit (48) to rearrange a time slot of a digital voice signal (PSHW) input from the outside and outputting it, and inputting the second clock (4MHz) to rearrange the time slot of the voice channel to be input and after that, outputting it to the outside; a matching unit (42) rearranging the signaling signal to be input from the outside according to a control of the central processing unit (48) to output it, and matching data to be input and output from/to the outside; a PCM matching unit (44) inputting outputs of the switching unit (41) and the matching unit (42) to form a frame according to a third clock (2MHz) and outputting it, and inputting the voice signal from the outside to output it to the switching unit (41); a decoding unit (43) decoding an address signal (LS 3:0)input from MLIB-B through the matching unit (42) to generate a circuit pack enable signal and retransmitting it to the MLIB-B through the matching unit (42), and decoding a control signal input (SI 15:0 , /RD 0:1)from the MLIB-B through the matching unit (42) to generate a subscriber enable signal and transmitting it to the subscriber through the switching unit (41) and the PCM matching unit (44); and a clock supplying unit (45) extracting a reference clock from the PCM matching unit (44) to generate the second and the third clocks and outputting them.
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