A signaling protocol for parallel access of a bus in a multiprocessor system (IMPROVED SIGNALING PROTOCOL FOR CONCURRENT BUS ACCESS IN A MULTIPROCESSOR SYSTEM)

摘要

The enhanced signaling protocol for the multiprocessor system 10 enables parallel access to the common system bus 18 during I / O bus access. This reduces the idle time of the system bus without causing the complexity of the system bus architecture, which can reduce the overall bus bandwidth increase. The enhanced bus architecture is a system-generated I / O bus (not shown) to indicate to all processors 12 that the I / O bus 20 is in use and all other I / O requests must be maintained until the current transaction is completed. Beji (IOBUS_-BSY-) signal. By preventing other processors 12 from performing I / O requests, the system bus 18 does not need to hold idle and can be used for transactions between memory processors and between processor processors during use of the I / O bus 20. [ have. By reducing the idle time of the system bus 18, the overall performance of the system bus is greatly increased.