Semiconductor memory devices (Having Small Chip Size and Redundancy Access Time) with small chip size and redundancy access time

摘要

The present invention relates to a semiconductor memory circuit designed to prevent delay of redundancy access due to long wiring between a redundancy control circuit (redundancy fuse circuit) and a redundancy cell array and to increase chip area. The redundancy cell arrays 30-32 are arranged in a plurality of memory cell arrays 20-23 and the corresponding redundancy fuse circuits 80-82 are respectively arranged to form the lines of the redundancy word drivers 51-53. For example, when a damaged address is selected in the redundancy fuse circuit 80, the redundancy determination signal RDN stops all the sense amplifiers 40, 43, and 44. The redundancy control information RED1 instructs the redundancy word driver 51 and the sense amplifier controllers 41 and 42 to select the redundancy cell array 30. [