How to Minimize Worst Cache Miss Penalties for RISC with Irregular Instruction Format

摘要

According to the present invention, when the first instruction is at the edge of the line and two words are cache misses, the second word is configured to bypass the main memory from the main memory to the CPU, thereby reducing the worst miss penalty and at the same time the worst interrupt latency. A method for minimizing the worst cache miss penalty of RISC having an irregular instruction format characterized by reducing the error.