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Delayed exception emulation method and system in a digital computer system

机译:数字计算机系统中的延迟异常仿真方法和系统

摘要

A digital computer system containing a regular exception processing processor and a control subsystem is provided. The regular exception processing processor performs arithmetic processing under the control of an instruction. A regular exception handling processor is constructed according to the regular exception handling model, in which, if an exception condition occurs in relation to an instruction, the exception condition is handled in relation to that instruction. The regular exception handling processor also includes a pending exception indicator with a pending exception indication state and a no pending exception indication state. The control system provides a set of instructions to a regular exception processing processor to facilitate emulation of at least one instruction from the emulation application of at least one instruction from the emulation program. The emulation program is configured to be handled by a delayed exception handling processor configured according to a delayed exception handling model wherein if an exception is detected during the processing of an instruction, the exception condition is handled with respect to the subsequent instruction. A series of commands provided by the control system during emulation of an emulation program instruction may include: (i) determining if the pending exception indicator is in a pending exception indication state, and if so, handling the pending exception, (Ii) performs a processing operation according to the emulation processing instruction, and (iii) if an exception condition is detected during the processing operation, the exception condition is notified to the subsequent emulation program instruction Controls the regular exception processing processor to call an exception handler according to the processor's commutation exception handling model to condition the pending exception indicator to a pending exception indication to be processed during processing operations on the processor.
机译:提供了一种包含常规异常处理处理器和控制子系统的数字计算机系统。常规异常处理处理器在指令的控制下执行算术处理。根据常规异常处理模型构造常规异常处理处理器,其中,如果相对于指令发生异常条件,则相对于该指令处理异常条件。常规异常处理处理器还包括具有未决异常指示状态和未决异常指示状态的未决异常指示符。控制系统向常规异常处理处理器提供一组指令,以促进来自仿真应用的至少一个指令的仿真,来自仿真程序的至少一个指令的仿真。该仿真程序被配置为由根据延迟的异常处理模型配置的延迟的异常处理处理器来处理,其中,如果在指令的处理期间检测到异常,则针对随后的指令来处理异常条件。由控制系统在仿真程序指令的仿真期间提供的一系列命令可以包括:(i)确定未决异常指示符是否处于未决异常指示状态,如果是,则处理未决异常,(Ii)执行(iii)如果在处理操作过程中检测到异常条件,则将该异常条件通知给后续的模拟程序指令。控制常规异常处理处理器根据处理器的调用来调用异常处理程序。换向异常处理模型,将待处理异常指示符条件化为待处理异常指示,以在处理器上进行处理操作期间进行处理。

著录项

  • 公开/公告号KR970062898A

    专利类型

  • 公开/公告日1997-09-12

    原文格式PDF

  • 申请/专利权人 리 페치;

    申请/专利号KR19970004632

  • 申请日1997-02-15

  • 分类号G06F9/455;

  • 国家 KR

  • 入库时间 2022-08-22 03:16:23

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