hochgeschwindige, hochleistende nulldetektorschaltung with parallel processing

摘要

A zero detection circuit operates to detect whether or not the result of addition/subtraction between a pair of binary numbers each composed of a plurality of bits becomes zero in all the plurality of bits. The zero detection circuit comprises a logic circuit receiving the pair of binary numbers A and B for generating a zero discrimination signal when anyone of the following four conditions is satisfied for each pair of bits of the same digit of the pair of binary numbers A and B: a first condition : if (Ai, Bi) = (0,0), (Ai+1, Bi+1) = (0,0); a second condition : if (Ai, Bi) = (0,0), (Ai+1, Bi+1) = (1,1); a third condition : if (Ai, Bi) = (1,1), (Ai+1, Bi+1) = (0,1) or (1,0); and a fourth condition : if (Ai, Bi) = (1,0) or (0,1), (Ai+1, Bi+1) = (1,0) or (0,1) where i is a natural number indicative of the digit place of the pair of binary numbers A and B.