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Method and structure for use in static timing verification of synchronous circuits

机译:用于同步电路的静态时序验证的方法和结构

摘要

A universal synchronization element is used in a static timing verification system to represent selected combinational primitive elements, synchronous primitive elements and external primitive elements in the user's synchronous digital circuit. Each of these digital circuit element in a user's digital circuit design is represented by a corresponding universal synchronization element having a propagation time characteristic equivalent to the digital circuit element and a stable time characteristic equivalent to the digital circuit element. The propagation and stable time characteristics are defined in relation to a clock signal for the digital circuit element in the user's circuit that the universal synchronization element represents. The universal synchronization element does not a fixed timing relationship between the signals on its input and output terminals. The adjustment of stable interval starting and end times and the propagation interval starting and end times is sufficient to represent the timing characteristics of circuit element with the universal synchronization element of this invention.
机译:在静态时序验证系统中使用通用同步元素来表示用户的同步数字电路中的选定组合基本元素,同步基本元素和外部基本元素。用户数字电路设计中的这些数字电路元件中的每一个都由具有与数字电路元件等效的传播时间特性和与数字电路元件等效的稳定时间特性的对应通用同步元件表示。相对于通用同步元件代表的用户电路中数字电路元件的时钟信号定义传播和稳定时间特性。通用同步元件在其输入和输出端子上的信号之间没有固定的时序关系。稳定间隔开始和结束时间以及传播间隔开始和结束时间的调整足以表示具有本发明的通用同步元件的电路元件的定时特性。

著录项

  • 公开/公告号US5579510A

    专利类型

  • 公开/公告日1996-11-26

    原文格式PDF

  • 申请/专利权人 SYNOPSYS INC.;

    申请/专利号US19930095627

  • 发明设计人 ALBERT R. WANG;RICHARD RUDELL;

    申请日1993-07-21

  • 分类号G06F17/00;

  • 国家 US

  • 入库时间 2022-08-22 03:11:02

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